1. Field of the Invention
The present invention relates to an image scanning device arranged to use a one-dimensional CCD sensor.
2. Description of the Related Art
Recently, an image scanning device has been widely used as means for inputting a text or a graphic data to a computer or inputting a data to a digital copier or a facsimile.
The image scanning device is arranged to apply an intense beam from a light source to a manuscript surface to be read and to form on an image sensor the beam reflected from the manuscript surface as an image through the effect of an optical system. The image sensor operates to photoelectrically convert the reflected beam into a voltage level proportional to intensity of the reflected beam, concretely, tone of the manuscript in a pixel-by-pixel manner for reading an image. The read analog signal is amplified and converted into a digital signal through the effect of an analog-to-digital converter. Then, the converted digital signal is transferred to the system.
The image sensor, in general, is a one-dimensional CCD sensor having pixels arranged on one line.
FIG. 15 is a general schematic view showing a scanning device.
A scanning device 10 comprises a glass table 12 on which a manuscript sheet 11 is to be placed, a light source 13 located under the glass table 12, an optical unit 14 having a mounting board 15 for mounting a CCD sensor 20, a mounting board 16 for mounting an analog processing circuit and a control circuit, a signal cable 21 connecting both of the mounting boards 15 and 16 with each other, and a cabinet 22. The optical unit 14 is provided with a mirror 18, a lens 19, a CCD sensor (CCD element) 20, and the mounting board 15. In addition, a numeral 17 denotes a pulse motor for moving the optical unit 14. The light source 13 performs a way of condensing light as shown in FIG. 16.
In FIGS. 15 and 16, during the scan, the beam emitted from the light source 13 passes through the glass table 12 to a manuscript sheet 11. The beam reflected on the manuscript sheet 11, again, passes through the glass table 12 and then is reflected on the mirror 18. The beam reflected on the mirror 18 is condensed through the lens 19 and then is applied to a light-receptacle surface of the CCD sensor 20.
FIG. 17 is a block diagram showing the CCD sensor used in the scanning device. S.sub.1, S.sub.2, . . . , S.sub.N denote photodiodes, each serving as a light receptor. AS.sub.1, AS.sub.2, . . . , AS.sub.N each denote an analog shift register (CCD) for shifting out an analog output of the light receptor. TGATE denotes a transfer gate for transferring an analog output of the light receptor to the analog shift register. OB denotes an output buffer. .phi..sub.T denotes a transfer pulse. .phi..sub.1 and .phi..sub.2 denote transfer clocks to the shift register. .phi..sub.R denotes a reset clock. VOUT denotes a CCD output.
The voltages generated in the light receptors S.sub.1, S.sub.2, . . . , S.sub.N are transferred to the analog shift register in synchronous to the transfer pulse .phi..sub.T. The resister operates to sequentially shift data in synchronous to the transfer clocks .phi..sub.1 and .phi..sub.2 and output the data for each one pixel at an output terminal of the shift register.
The output from the shift register is fed to an output buffer OB. The reset pulse .phi..sub.R is applied to the output buffer OB at each of the light receptors contained in the CCD.
The output VOUT from the output buffer OB is picked out as an output of the CCD sensor.
The black level of the output VOUT of the CCD sensor normally keeps an electric potential of about 3 to 6 V in the floating state. To keep the black level at a constant potential, a clamp circuit is used.
FIG. 18 is a block diagram showing a CCD sensor having two output channels. In FIG. 18, S.sub.1, S.sub.2, . . . , S.sub.2n each denote a light receptor. OSR.sub.1, OSR.sub.2, . . . , OSR.sub.n denote odd shift registers for shifting out the analog outputs of the light receptors located in odd rows. OTG denotes an a transfer sate for transferring the analog outputs of the light receptors located in odd rows to the shift registers ranged in odd rows. ESR.sub.1, ESR.sub.2, . . . , ESR.sub.n denote shift registers ranged in even rows, for shifting out the analog outputs of the light receptors located in even rows. ETG denotes a transfer gate for transferring the analog outputs of the light receptors ranged in even rows to the shift registers located in even rows. OBUF denotes a buffer amplifier for odd rows. EBUFF denotes a buffer amplifier for even rows. SH denotes a start pulse for starting a shift operation of the shift register. .phi..sub.10, .phi..sub.20, .phi..sub.1E and .phi..sub.2E denote transfer pulses. .phi..sub.RO and .phi..sub.RE denote reset pulses. OCCDOUT denotes a CCD output of the light receptors on the column side. ECCDOUT denotes a CCD output of the light receptors on the even side. As an example, if n is set as n=1024, the resulting CCD sensor has 2048 elements.
Further, FIG. 19 is a block diagram showing a conventional scanning device. In FIG. 19, a numeral 60 denotes a CCD driving circuit. The output of the CCD driving circuit 60 is connected to an input of the buffer 78 through a level-shift capacitor 80. The input of the buffer 78 is connected to a 5-volt power supply through a clamping transistor 81. The output of the buffer 78 is connected to an input of an analog-to-digital converter 75. The black level of the CCD output is fixed at 5 volts through the effect of the level-shift capacitor 80 and the clamping analog switch 81.
A numeral 51 denotes a control circuit for outputting various control clocks .phi..sub.T, .phi..sub.1, .phi..sub.2, .phi..sub.R, T.sub.CLAMP, and T.sub.AD. The clocks .phi..sub.T, .phi..sub.1, .phi..sub.2 and .phi..sub.R are applied to the CCD driving circuit 60. The clock T.sub.CLAMP is applied to the transistor 81. The clock T.sub.AD is applied to an analog-to-digital converter 75.
In turn, the description will be oriented to the operation of the conventional scanning device. FIG. 20 shows several timings for signals, concretely, the driving signals .phi..sub.T, .phi..sub.1, .phi..sub.R, the CCD output signal VOUT, the clamp signal T.sub.CLAMP, the buffer output VO, and the driving signal T.sub.AD for an analog-to-digital converter. The VOUT output of the CCD driving circuit 60 is clamped at 5 volts through the effect of the capacitor 80 and the transistor 81. The clamped signal is amplified by the buffer 78 and then is outputted as a signal VO. The signal VO is converted into a digital signal DOUT through the effect of the analog-to-digital converter 75.
In FIG. 19, the analog-to-digital converter 75 may be assumed as a 8-bit converter. If the signal VO=+5 volts, the output DOUT (DOUT0, DOUT1, . . . , DOUT7) is; ##EQU1## That is, EQU DOUT.sub.K =0 (K=0, 1, . . . , 7)
If the signal VO=0 volt, the output DOUT is; ##EQU2## That is, EQU DOUT.sub.K =1 (K=0, 1, . . . , 7)
The analog-to-digital converter 75 operates to convert the analog buffer output VO into a digital signal at the leading edge of the clock T.sub.AD and then transfer the digital output DOUT to the host computer. The host computer reads the digital output DOUT at the trailing edge of the clock T.sub.AD.
In FIGS. 15 and 19, the signals .phi..sub.10 and .phi..sub.1E for driving the driving circuit 60 are generated from the signal .phi..sub.1. The signals .phi..sub.20 and .phi..sub.2E are generated from the signal .phi..sub.2. The transfer clock signals .phi..sub.1 and .phi..sub.2 are generated by the analog processing circuit 70 and the control circuit 51 and then fed to the CCD driving circuit through the signal cable 21. Thus, the signal is excessively delayed. If the long signal cable is used, the phases of the signals .phi..sub.1 and .phi..sub.2 are shifted on the long transfer way, thereby worsening the transfer efficiency of charges contained in the CCD sensor. FIG. 21a shows the phase-shifted signal waveform. FIG. 21b shows the signal waveform keeping a proper phase.
The reset pulses .phi..sub.RO and .phi..sub.RE to be sent to the CCD driving circuit are generated from the reset pulse .phi..sub.R. The reset pulse .phi..sub.R is produced by the analog processing circuit 70 and the control circuit 51 and is fed to the CCD driving circuit 60 through the signal cable 21.
The reset pulse .phi..sub.R made of fast clocks is adversely effected by the radio wave generated in the signal cable 21.
Moreover, when .phi..sub.R is being sent on a long transmission way, the time relation between .phi..sub.1 and .phi..sub.2 may be variable.
A reverse signal of .psi..sub.0 from which .phi..sub.1 and .phi..sub.2 are generated brings about radio wave noises in the signal cable.
If the CCD sensors are provided on the two channels for odd and even outputs for executing the fast processing, the outputs on the odd and the even sides from the CCD elements are independently converted into the digital signals through the corresponding analog-to-digital converters. Since, however, the analog-to-digital converters have their own analog-to-digital converting characteristics, it results in disadvantageously making periodic stripes in the signals.
The foregoing disadvantages inhibit to drive the CCD sensor at most several MHz.
Further, as shown in FIG. 16, the beam from the light source is widely dispersed with the reading line as a center. As such, the use part of the beam is quite small, which results in disadvantageously worsening the image quality.
The time consumed for one period of the buffer output VO is calculated with reference to FIG. 22. The time is 400 nsec. This is because
a width t1 of the reset signal .phi..sub.R normally needs as long as 50 nsec, PA1 a time t2 from the tail of the reset signal .phi..sub.R to the trailing edge of the clamp signal T.sub.CLAMP needs at least an interval of 50 nsec, PA1 a width t3 of the clamp signal T.sub.CLAMP needs at least 50 nsec or longer, PA1 a time t4 from the tail of the clamp signal T.sub.CLAMP to the start of the signal component of the buffer output VO needs at least an interval of 50 nsec, and PA1 a time width t5 from when the signal component of the buffer output VO is settled down to when the signal component to be converted from an analog to a digital signal is obtained needs an interval of 200 nsec. PA1 a light source for emitting a beam; PA1 a CCD circuit board having a CCD sensor; PA1 an optical unit for guiding the emitted beam from the light source to the CCD sensor; PA1 a CCD sensor driving circuit connected with the CCD circuit board with a signal cable; PA1 a clock generating circuit for generating a clock to be transferred to the CCD sensor; PA1 a reset pulse generating circuit for generating a reset pulse for resetting an output buffer of the CCD sensor; PA1 a clamp circuit for clamping an output of the CCD sensor; and PA1 an analog-to-digital converter for converting an analog signal into a digital signal, PA1 wherein the clock generating circuit is disposed on the CCD circuit board. PA1 a light source for emitting a beam; PA1 a CCD circuit board having a CCD sensor; PA1 an optical unit for guiding the emitted beam from the light source to the CCD sensor; PA1 a CCD sensor driving circuit connected with the CCD circuit board with a signal cable; PA1 a clock generating circuit for generating clocks to be transferred to the CCD sensor; PA1 a reset pulse generating circuit for generating a reset pulse for resetting an output buffer of the CCD sensor; PA1 a clamp circuit for clamping an output of the CCD sensor; and PA1 an analog-to-digital converter for converting an analog signal into a digital signal, PA1 wherein the reset pulse generating circuit is disposed on the CCD circuit board. PA1 a light source for emitting a beam; PA1 a CCD circuit board having a CCD sensor; PA1 an optical unit for guiding the emitted beam from the light source to the CCD sensor; PA1 a CCD sensor driving circuit connected with the CCD circuit board with a signal cable; PA1 a clock generating circuit for generating clocks to be transferred to the CCD sensor; PA1 a reset pulse generating circuit for generating a reset pulse for resetting an output buffer of the CCD sensor; PA1 a clamp circuit for clamping an output of the CCD sensor; and PA1 an analog-to-digital converter for converting an analog signal into a digital signal, PA1 wherein the CCD sensor driving circuit comprises a fast clock generator for feeding clocks to a CCD element at fast speed and a voltage attenuator for attenuating a voltage of the fast clocks. PA1 a light source for emitting a beam; PA1 a CCD circuit board having a CCD sensor; PA1 an optical unit for guiding the emitted beam from the light source to the CCD sensor; PA1 a CCD sensor driving circuit connected with the CCD circuit board with a signal cable; PA1 a clock generating circuit for generating a clock to be transferred to the CCD sensor; PA1 a reset pulse generating circuit for generating a reset pulse for resetting an output buffer of the CCD sensor; PA1 a clamp circuit for clamping an output of the CCD sensor; and PA1 an analog-to-digital converter for converting an analog signal into a digital signal, PA1 wherein the optical unit includes a light condensing circuit for condensing the beam emitted from the light source to a front point of the light source, the light source irradiating the beam on a manuscript surface. PA1 a light source for emitting a beam; PA1 a CCD circuit board having a CCD sensor; PA1 an optical unit for guiding the emitted beam from the light source to the CCD sensor; PA1 a CCD sensor driving circuit connected with the CCD circuit board with a signal cable; PA1 a clock generating circuit for generating a clock to be transferred to the CCD sensor; PA1 a reset pulse generating circuit for generating a reset pulse for resetting an output buffer of the CCD sensor; PA1 a clamp circuit for clamping an output of the CCD sensor; PA1 an analog-to-digital converter for converting an analog signal into a digital signal; PA1 an actuating circuit for actuating the reset means and the clamp circuit one time for a plurality of outputs of the CCD sensor; PA1 a first latch circuit for latching an output of the analog-to-digital converter; PA1 a second latch circuit for latching for latching an output of the first latch circuit; and PA1 a subtracting for subtracting the output of the second latch circuit from the output of the first latch circuit.
Hence, the time required for one period of the buffer output VO is; EQU t1+t2+t3+t4+t5=400 nsec
That is, the time for one period needs twice as long as a time width t5 of the signal component. This is because the signal is reset and clamped at each one CCD output. This limits a reading speed of the scanning device arranged to use the CCD sensor, thereby making it impossible to do fast scanning.